Digital Pulse Width Modulator Architecture Research Articles

High resolution digital pulse width modulator architecture using reversible synchronous sequential counter and synchronous phase-shifted circuit

High resolution digital pulse width modulator architecture using reversible synchronous sequential counter and synchronous phase-shifted circuit

Digital Pulsewidth Modulation (DPWM) Using Direct Digital Synthesis

Wide-bandgap semiconductor power devices are being adopted to increase efficiency and switching frequency for power converters. This requires a demand for higher resolution digital pulsewidth modulation (DPWM) in digitally controlled power converters. This is because, in a digitally controlled dc–dc converter, steady-state limit-cycle oscillations can exist if the resolution of DPWM is less than the ADC resolution. This article proposes a cost-competitive, high-performance, functionally integrated with a small package-sized, a complete direct digital synthesis-based DPWM architecture to achieve a high resolution, linear, monotonic behavior, and extremely fast frequency hopping ability. This article presents a detailed analysis of the new DPWM architecture. Simulation and experimental results are presented to verify the analysis. This article also discusses the various advantages and numerous applications addressed by the proposed method.

Design of digital pulse width modulator architecture with digital PID controller for DC-DC converter using FPGA

A digital pulse width modulation architecture (DPWM) along with digital proportional integral derivative (PID) controller to control the DC-DC converter is presented in this paper. Difference between the actual output voltage and the reference voltage is calculated as error value. The look up table is created for PID controller to store the duty cycle ratio and the error value of power converters. Multipliers used in conventional algorithms are replaced by look up tables in the proposed work that enable the compact and low power implementation of digital controllers. DPWM architecture is developed with gray logic against the binary logic used in traditional DPWM architectures. Usage of gray counter also leads to low power consumption in the DPWM architecture. The proposed architecture is designed using Verilog hardware language and realized using field programmable gate array. PWM signals with varying duty cycle percentage can be derived from the proposed architecture. The generated PWM signal can control the switching condition of power converter to regulate the output voltage. Duty cycle percentage ranging from 16 to 96% can be developed with the proposed architecture. Simulation and experimental results of the architecture validate the proposed architecture. PWM signal with maximum operating frequency of 59.49 MHz and 60.22 MHz for SPARTAN 3A and SPARTAN 3E respectively can be generated with the proposed architecture.

A Delay-Line DPWM Architecture With Compensation Module and Delay-Adjustable Unit Based on DLL

Due to the increasing resolution, the duty cycle in digital pulsewidth modulation (DPWM) is affected by the variation of external clock frequency or temperature, and the time error becomes larger and larger, even reaches a few nanoseconds. The increment of the duty cycle will affect the regulation performance of the converter and the output of DPWM. In this article, a delay-line DPWM architecture with a compensation module and a delay-adjustable unit based on delay-locked loop is proposed. The delay-adjustable unit is realized by using a multiplexer and some delay paths with different delay times, which effectively reduces the influence of temperature or the frequency changes from the input clock. Furthermore, a time compensation method is used to reduce the error generated by the critical path delays. A 10-bit DPWM with 781-kHz switching frequency is achieved on A-7 (xc7a100tfgg484) Xilinx FPGA, and the time error of the architecture decreases to around 500 ps. The duty cycle range is from 1.63% to 98.44%.

Single Inductor-Multiple Output DPWM DC-DC Boost Converter with a High Efficiency and Small Area

In this paper, a small-area and high-efficiency single-inductor multiple output (SIMO) boost converter with digital pulse-width modulation (DPWM) is proposed. The DPWM comprises a delay line using interlaced hysteresis delay cells (IHDCs) that occupy a small area while consuming a low power amount. These proposed IHDCs are applied to replace the conventional delay cells of the prior works for both the power and area reductions. Regarding the DC-DC converter, this technique comprises fewer digital blocks in the feedback path compared with the conventional DC-DC converter, and the DPWM architecture uses IHDCs. The purpose of the digital limiter block is to concede some helpful code for the DPWM. The IHDC topology used for delay in DPWM is of the simplest architecture. The high-side power switch gate drivers need individual phases which are generated by phase control. The Complementary Metal Oxide Semiconductor (CMOS)-fabrication process is 55 nm, with a standard supply voltage of 1.8 V and outputs of 2.2 and 2.4 V. The chip area is approximately 170 × 190 µm and its efficiency is 94.4%.

Window-Masked Segmented Digital Clock Manager-FPGA-Based Digital Pulsewidth Modulator Technique

This paper presents a new digital pulsewidth modulator (DPWM) architecture for field programmable gate array (FPGA)-based systems. The design of the proposed DPWM architecture is based on fully utilizing the digital clock manager (DCM) resources available on new FPGA boards. Furthermore, this architecture will also window-mask the DCM operation to only a portion of the switching period in order to decrease power dissipation. This proposed digital modulator technique allows for higher DPWM resolution with lower power consumption, the primary barrier to high switching frequency operation. The presented technique relies on power-optimized resources already existing on new FPGAs, and benefits from the inherit phase-shifting properties of the DCM blocks, which help in simplifying the duty cycle generation. The architecture can be applied to achieve different numbers of bits for the DPWM resolution designed for different dc-dc applications. The suggested architecture is first simulated, implemented, and experimentally verified on a Virtex-4 FPGA board.

Electromagnetic Susceptibility Analysis on a Digital Pulse Width Modulator for SMPSs

In this paper, a digital pulse width modulator (DPWM) is analyzed from the point of view of susceptibility to radio-frequency interference (RFI). The chosen DPWM architecture is based on the hybrid delay-line/counter scheme commonly used in the digital control of switched-mode power supplies (SMPSs). This paper focuses on the DPWM performance degradation in the presence of electromagnetic interference (EMI), and for this purpose a DPWM with time resolution down to 350 ps has been designed and manufactured in a standard 0.35- mum complementary metal-oxide semiconductor technology. Measurements and analytical analyses are presented for both EMI effects on the internal generated clock signal and on the PWM duty-cycle precision. The immunity degradation mechanisms are investigated by means of an analytical approach, demonstrating that the PWM susceptibility is more strictly related to its functional design rather than to the implemented topology. The effects of clock and duty-cycle jitter induced by RFIs are finally verified using a simulation model on a digitally controlled buck converter, highlighting the importance of such issue on steady-state performances of SMPSs.